1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to performing read operations on memory cells in non-volatile memory.
2. Related Art
Semiconductor non-volatile memories (NVMs), and particularly flash electrically erasable, programmable read-only memories (EEPROMs), are widely used in a range of electronic equipment from computers, to telecommunications hardware, to consumer appliances. The flash EEPROM is encountered in numerous configurations. In particular, a floating gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, “floating”). In another configuration, a charge storage layer comprising nanocrystals as the charge storage mechanism is used in place of the floating gate. The nanocrystals function as isolated charge storage elements.
An NVM typically has millions of memory transistors that are in a programmed or erased state. A transistor is programmed or erased by adjusting the threshold voltage of the transistor through some form of movement of charges into the gate oxide so that if the gate and source of the transistor are biased to a pre-determined voltage and a pre-determined current is impressed on the drain of the transistor, the drain current of the transistor will be a measure of the programmed or erased state of the transistor as indicated in FIG. 1.
The difference between the program and erase voltages for the transistors in the array will be dependent on process variations. In general if all transistors are erased and the gate voltages are measured at a set drain current, then the result roughly will be a Gaussian distribution as shown in FIG. 2. For some NVM's the mean of the distribution will be a low voltage and the highest voltage in the distribution is called the “least erased level” (LEL). For those NVM's the mean of the distribution of programmed transistors will be a higher voltage and the lowest voltage in the distribution is called the “least programmed level” (LPL) as shown in FIG. 3. After a transistor is programmed (or erased), the gate voltage is checked to insure the gate voltage is greater than the LPL (or less than the LEL). Verification voltages, called the “Erase Verify” (EV) and “Program Verify” (PV) voltages are selected to ensure that a transistor is successfully erased or programmed respectively. The EV is slightly greater than the LEL and the PV is slightly less than the LPL, as shown in FIG. 4.
During normal operation, to determine if the transistor is programmed or erased, the gate voltage is driven to a pre-determined READ voltage and its drain current is compared against a reference current by a sense amplifier. The READ voltage is generally a value greater than the LEL voltage and less than the LPL voltage. The selection of the READ voltage can be difficult because the difference between the LEL and the LPL may not be large and cannot be determined a priori. In addition, the LEL and LPL will shift during the life of the NVM. Finally, other design constraints such as sense amplifier resolution will constrict the usable window between the LEL and LPL. Selection of the READ, PV, and EV voltages requires a great deal of effort. Typically a large number of NVM arrays from a large number of wafers are operated and tested for a considerable time in an effort to predict the lifetime performance of the NVM. FIG. 5 shows the variation in the erase and program distributions that are caused by processing variation, aging and cycling. This is an expensive undertaking and greatly extends the development time of NVM technology.
As devices continue to become smaller with advances in semiconductor device technology, the performance of the individual memory cells has become more important. The read function and threshold voltage variation in particular suffer with reduced device size. Accordingly, it is desirable to improve upon the issues raised above concerning reading an NVM memory.